1. Field of the Invention
The invention relates to memories in integrated circuit form, and more particularly to reading circuits that can be used to detect the state of the cells of the memory.
The invention shall be described with reference to electrically programmable non-volatile memories (EEPROM, EPROM, flash EPROM) although it is applicable to other types of memories, both volatile and non-volatile.
The memories are organized in networks of cells, the cells of a same column being connected to a bit line, and the cells of a same row being connected to a word line. The bit line enables the transmission of an information element on the state of a memory cell located at the intersection of this bit line and a selected word line.
The reading circuits are connected to bit lines, possibly by means of a multiplexer if there are several bit lines for one reading circuit. Hereinafter, we shall consider a single reading circuit, assumed to be connected to a single bit line, in order to simplify the explanations.
2. Description of the Prior Art
The general principle of a reading circuit is shown in FIG. 1, and its operation shall be explained hereinafter. It is assumed that the memory is an EEPROM memory, it being possible for the cells to have a blank state in which they let through an electrical current, and a programmed state in which they counter the passage of the current. To read the information, it is sought to detect the presence of a load current or discharge current of the bit line connected to the cell to be read. A current such as this exists if the cell is blank, while it does not exist if the cell is programmed.
To detect the current, a reference line similar to the bit line is used, so as to work in differential mode. The reference line conducts a reference current during the reading phase. In a precharging phase prior to the reading phase, the bit line and the reference line are precharged to a potential that may be of the order of 1 volt. Then the reading phase takes place, and the bit line discharge current is compared with the reference line discharge current. This makes it possible to determine whether the selected cell is blank or programmed. Preferably, a current/voltage converter is used to convert the bit line discharge current into a voltage so as to enable the use of a voltage differential amplifier to carry out the comparison.
FIG. 1 shows a simplified view of an exemplary prior art reading circuit.
A memory cell CM, located at the intersection of a word line WL and a bit line BL may be selected by the word line, and it then delivers an information element on the bit line. The bit line BL is precharged in voltage, in a precharging phase, by a precharging transistor T1 which has the function of giving a precharging current to the bit line, while restricting the precharge potential to a determined value, preferably in the region of one volt.
A reference line LR, having characteristics very similar to those of the bit line, notably from the viewpoint of the parasitic capacitances, is also precharged to a voltage value of about one volt by a precharging transistor T2. During the reading phase, this reference line consumes current equivalent to the current consumed by a blank memory cell. The reference line may be the bit line of a column of blank reference cells addressed by the same word lines as the cells to be read.
The transistors T1 and T2 are preferably N channel transistors, and their source is connected to the bit line and to the reference line respectively. To simplify the description, the gates of the transistors T1 and T2 are shown as being connected to a bias voltage source V1. The value of the voltage V1 defines the upper limit of the voltage for the precharging of the lines LR and BL.
To read the state of the cells, a comparison shall be made between the current consumed by the bit line and a reference current. More specifically, the current consumed by the bit line will be compared with a reference current which is a fraction of the current normally consumed by a blank cell.
To this end, the drains of the transistors T1 and T2 are supplied by the two arms of a current mirror with a copying ratio k that is smaller than 1. The first arm of the mirror has a copying transistor T3. The second arm has a reference transistor T4. The copying transistor tends to copy the current that flows in the reference transistor. The copying ratio k is the ratio of the geometries of the transistors, and preferably it is seen to it that the ratio k is smaller than unity, preferably 1/2.
The copying transistor T3 is a P channel transistor having its source connected to the high voltage supply terminal of the circuit (terminal A); this terminal is generally at a level of about +5 volts above a low voltage supply terminal. The drain of the copy transistor is connected to the drain of the first precharging transistor T1.
In the same way, the reference transistor T4 is a P channel transistor, with a greater geometry than T3, the source of which is connected to the terminal A and the drain of which is connected to the drain of the second precharging transistor T2.
The gates of the transistors T3 and T4 are joined, and the gate of the reference transistor is connected to its drain (in a diode assembly). There is therefore a standard current copying diagram.
A differential amplifier AD has its inputs connected to the drains of the transistors T3 and T4 and therefore measures the difference between the potentials at these two drains. This difference is zero if the ratio of the currents in T3 and T4 is the ratio k of the geometries. It differs from zero if the ratio of the currents differs from k. The output of the amplifier AD gives a signal which indicates whether the ratio of the currents is greater than or smaller than k.
Finally, a balancing transistor T5 is placed in order to zero-set the differential input voltage at the terminals of the differential amplifier, in a balancing phase that follows the precharging phase and precedes the reading phase. This balancing phase enables the differential voltage difference at the input of the amplifier AD to be reduced to a value that is as close as possible to zero irrespectively of the logic state read in a memory cell at the previous reading phase. The transistor T5 is, for example, an N channel transistor that is made conductive during a balancing phase EQ.
Among the qualities that are expected of a reading circuit, there are notably the obtaining of sufficient speed for the precharging, balancing and reading phases, this speed being furthermore related to the sensitivity of the reading, i.e. the capacity of the circuit to detection small variations in current.